Field
The present disclosure relates generally to high-speed data communications interfaces, and more particularly, multi-wire, multi-phase data communication links.
Background
In the field of high-speed serial communication, demand for ever-increasing data rates continues to grow. Many conventional high-speed serial interface systems use non-return to zero (NRZ) data encoding with separate data and clock signals. This separation of the data and clock signals, however, typically results in skew between the two signals, limiting the maximum possible link data rate of the interface.
Typically, de-skewing circuitry is used at the receiving end of the serial interface to eliminate skew between the data and the clock signals. Consequently, both the real estate requirements and the link start-up time of the serial interface are increased, with the latter becoming disadvantageous when the interface is being used intermittently at a low duty cycle to minimize system power consumption.
Other conventional serial interface systems are more immune to skew by using data and strobe signals, but still suffer from skew problems when operating at high speeds.
Additionally, certain integrated receiver devices are typically built with slower logic because they have larger feature sizes in order to drive high voltages. This is the case, for example, for integrated liquid crystal display (LCD) Controller-Driver circuits that are used to drive LCD panels. As such, it would be difficult to implement a high-speed serial interface for such devices using conventional systems.
What is needed therefore is a high-speed serial interface that resolves the above-described problems of conventional serial interface systems. Further, a high-speed serial interface with increased capacity and reduced power consumption relative to conventional systems is needed.